1. Field of the Invention
An aspect of the present invention relates to a method of manufacturing a semiconductor device provided with a laminated gate electrode and a semiconductor device.
2. Description of the Related Art
In recent years, in the field of semiconductor storage devices, miniaturization of the cell structure is advanced rapidly in association with increase in demand of bulk storage devices such as flash memory devices. On the other hand, the same level or a higher level of the electric property of the device elements or the inter-element wirings as those in the previous generation is required. As a gate electrode of the semiconductor storage element as described above, a structure in which metals are alloyed on the gate electrodes to lower the resistance of the wirings connected to the gate electrodes is generally employed (for example, see JP-2002-231835-A).
A manufacturing method disclosed in JP-2002-231835-A will be described below. An element isolation film is formed on a semiconductor substrate to define linear active areas formed in parallel. A gate insulating film is formed on the active areas of the semiconductor substrate, and a silicon floating gate layer is formed on the gate insulating film. The silicon floating gate layer is patterned to form an intermediate pattern of a floating gate. Then, an isolation insulating film (ONO film) and a doped polysilicon control gate layer are formed. The polysilicon control gate layer, the isolation insulating film, and the intermediate pattern are etched in the direction perpendicular to the direction of formation of the active areas, thereby forming a plurality of gate lines (word lines) perpendicular to the direction of formation of the active areas. Then, a spacer is formed and a source/drain area having a LDD (Lightly Doped Drain) structure is formed to configure the MOS transistor, and then an inter-layer insulating film is formed thereon. Then, part of the inter-layer insulating film is removed to expose the control gate pattern. Then, the metal such as cobalt or titanium is processed on the control gate pattern to form a metal silicide layer.
However, in association with the miniaturization of elements and the tightening of the design rule, the cell wiring pitch is reduced, and hence the width of the gate electrode is also reduced. When the cell wiring pitch is reduced, the width between the gate electrodes, and hence the embedding property of the inter-electrode insulating films embedded therebetween are deteriorated, so that seams are generated in the inter-electrode insulating films. On the other hand, when the width of the gate electrodes is reduced, the resistance of the word lines, which are connected to the gate electrodes, increases. Consequently, the transmission rate of the signals to be transferred in the word lines is lowered. In order to reduce the resistance of the wirings, it is considered to expose the side walls of the control gate by deeply etching back the inter-electrode insulating film, and to alloy metals on the exposed side walls. However, when the etching amount is increased, there arises fear that the seams generated in the inter-electrode insulating films are exposed and expanded.
When the seams in the inter-electrode insulating films are expanded, the metal is apt to enter the seams when the metal is formed on the control gate pattern. Then, even when the etching process is performed in the removing process, the metal entered into the inter-electrode insulating film cannot be removed, so that there arises a fear of short-circuit between the gate electrodes.